This application claims the benefit of Korean Patent Application No. 1999-67848, filed on Dec. 31, 1999, under 35 U.S.C. xc2xa7119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a polycrystalline silicon layer of a switching element, for example, a thin film transistor (TFT).
2. Description of Related Art
A thin film transistor (TFT) includes an insulating layer, a passivation film, electrode layers and a semiconductor layer. The insulating layer is made of SiNx, SiO2, Al2O3 or TaOx. The passivation film is made of a transparent organic insulating material or a transparent inorganic insulating material. The electrode layer includes a gate electrode, a source electrode and a drain electrode and is made of a conductive metal such as Al, Cr or Mo. The semiconductor layer acts as a channel region along which charges flow and is made of amorphous silicon or polycrystalline silicon.
A process of manufacturing the semiconductor layer using the amorphous silicon can be performed at a low temperature of about 350xc2x0 C. and thus is relatively simple. However, since a field effect mobility of the amorphous silicon layer is as low as 2 xe2x96xa1/Vsec, thus, switching characteristics of the TFT and an incorporation characteristics between a driving circuit and the TFT are not so good.
Meanwhile, the polycrystalline silicon layer is much more excellent in response speed than the amorphous silicon layer. The polycrystalline silicon layer has as a high field effect mobility as about 20 xe2x96xa1/Vsec to about 550 xe2x96xa1/Vsec. A switching speed of the TFT depends on the field effect mobility. That is, a switching speed of the polycrystalline silicon layer is 100 times as fast as that of the amorphous silicon layer. This comes from that the polycrystalline silicon layer is more in grain number and is smaller in defect than the amorphous silicon layer.
A method of manufacturing the polycrystalline silicon layer includes an eximer laser annealing technique, a solid phase crystallization (SPC) technique, and a metal induced crystallization (MIC) technique.
The eximer laser annealing technique is performed at a low temperature and, thus a low-cost glass substrate is used. The TFT manufactured using the eximer laser annealing technique has a field effect mobility more than 100 xe2x96xa1/Vsec and thus is excellent in operating characteristics.
The solid phase crystallization technique is one which amorphous silicon is crystallized at a high temperature of more than 600xc2x0 C. Since a crystallization is performed at a solid phase, a grain has many defects such as a micro-twin, a dislocation and the like, whereupon a grade of a grain is low. In order to compensate for this problem, a thermal oxidation film of about 1000xc2x0 C. is used as a gate insulating layer. Therefore, since a high-cost material such as quartz is used for the substrate, there is a problem that a production cost is high.
The metal induced crystallization technique is one that a crystallization is performed in such a way that a metal layer is deposited on the amorphous silicon layer and then a heat treatment is performed. The metal layer serves to lower an enthalpy of the amorphous silicon layer. As a result, a process is possible at a low temperature of about 500xc2x0 C. However, a surface state and electrical characteristics are not so good. This technique also causes many defects in grain.
The polycrystalline silicon layer manufactured using the techniques described above can obtain grains while the silicon of a liquid state is cooled from a silicon seed at the beginning stage of crystallization. In case that a grain of the silicon grows laterally, large-sized grains can be obtained. If a distance between adjacent silicon seeds is greater than a maximum silicon growth distance, the silicon grain that performs a lateral growth centering the silicon seed grows maximally, and then a small-sized grains are created on a region of a liquid state due to a nucleus generated by a super-cooling. However, a distance between adjacent silicon seeds is smaller than a maximum silicon growth distance, a lateral growth occurs centering a seed, forming grain boundaries, whereby the polycrystalline silicon layer having large-sized grains is formed. As described above, in order to obtain the excellent TFT, the large-sized grains should uniformly be arranged while forming the grain boundaries.
FIGS. 1A to 1C are plan views illustrating a crystallization process of a polycrystalline silicon layer. A distance between the two adjacent silicon seeds 11 is smaller than a maximum grain growth distance, but it is desirable that the silicon seeds 11 are uniformly distributed. The silicon grains 13 of a liquid state grow laterally centering on the silicon seed 11 and complete their growth while forming grain boundaries 15.
Hereinafter, a crystallization process of the polycrystalline silicon layer using the eximer laser annealing technique according to a conventional art is explained in detail.
FIG. 2 is a perspective view illustrating a configuration of a polycrystalline silicon crystallization equipment using the eximer laser annealing technique. The equipment includes a laser beam device (not shown), a mask 33, and a projection lens 35. The projection lens 35 is arranged over a substrate 31, and the mask 33 is aliened with the projection lens 35. When a laser beam 37 is projected from the laser beam device toward the mask 33, the laser beam 37 becomes incident along the mask pattern. The laser beam incident to the mask 33 passes through the projection lens 35 and is concentrated on a substrate 31 having an amorphous silicon layer formed thereon, whereby polycrystallization of the amorphous silicon layer is performed according to the mask pattern.
At this point, a growth of the polycrystalline grain is controlled by a shape and an energy density of the laser beam and a temperature and a cooling speed of the substrate. A silicon grain during a crystallization process is divided into three regions: a low energy density region; an intermediate energy density region; and a high energy density region. The low energy density region is a partially melt region. That is, the lower energy density region is one which only a lower portion of the silicon layer is not melt and a silicon melting depth is smaller than a thickness of the silicon layer and a grain diameter is smaller than a thickness of the silicon layer because seeds on the lower portion of the silicon layer grow vertically.
The intermediate energy density region is an almost completely melt region. That is, the intermediate energy density is one which only part of seeds on the lower portion of the silicon layer is not completely melted. Except for part of seed on the lower portion of the silicon layer, almost part of the silicon layer is completely melted. This region is also a region that a lateral growth is possible centering on the seeds.
The high energy density region is one that even the lower portion of the silicon layer is completely melted.
A crystallization method using the polycrystalline silicon crystallization equipment of FIG. 2 is as follows. The laser beam 37 is uniformed by predetermined means. Thereafter, a type of a laser beam that will be formed on the substrate 31 is determined through the mask 33. A laser beam having a width of tens of xe2x96xa1 is formed through the projection lens 35. The substrate 31 arranged on a stage moves slowly at a speed of less than 1 xe2x96xa1/pulse, so that a crystallization is performed by the laser beam. The mask 33 has divided regions xe2x80x9cAxe2x80x9d, xe2x80x9cBxe2x80x9d, and xe2x80x9cCxe2x80x9d in shape of stripe.
FIG. 3 is a plan view illustrating a mechanism that the amorphous silicon layer is crystallized through the laser beam. At this time, in first and second crystallization steps 45, a lateral growth occurs by moving the substrate 31. At the second step, a grain boundary 41 of the first step moves and forms a new grain boundary 41a. Preferably, a high energy density for complete melting is used, and a width of the laser beam is smaller than twice of the maximum lateral growth distance.
After an n-th crystallization step, grains of the polycrystalline silicon that is crystallized by the lateral growth grows as large as a grain 43 and the grain boundary 41n is finally determined.
FIG. 4 is a plan view illustrating the semiconductor layer manufactured through the above-described method. The semiconductor layer 55 that will be formed between the source and drain electrodes 51 and 53 includes a plurality of polycrystalline silicon grains 55a. Since a width of the grain 55 is so small, for example, in a range of about 1000 xc3x85 to about 2000 xc3x85, the semiconductor layer 55 has a large number of grain boundaries 55b, which affects the charge flow between the source and drain electrodes to be lowered. This is because a trap level of charge occurs at the grain boundary 55b. Accordingly, as the number of the grain boundaries increases, electrical characteristics of the TFT become lowered.
To overcome the problems described above, preferred embodiments of the present invention provide a method of manufacturing a polycrystalline silicon layer having excellent electrical characteristics.
In order to achieve the above object, the preferred embodiments of the present invention provide a method of manufacturing a polycrysalline silicon layer, comprising: depositing an amorphous silicon layer on a substrate; patterning the amorphous silicon layer to form a semiconductor layer having saw-toothed portions at both sides; and scanning the semiconductor layer from the saw-toothed side portion using a laser beam to form a polycyrstalline silicon layer. The laser beam has a line shape elongated in a perpendicular direction to a scanning direction.